The present invention relates to a time base correction circuit employing clock response delay elements such as charge-coupled devices (CCD) which operate in response to clock pulses.
Time base correction circuits for correcting the same time base error present in two input signals in different frequency bands include circuits employing clock response delay elements such as CCDs as time base correction elements.
FIG. 1 shows a signal processing circuit of a video disk player equipped with such a time base correction circuit using CCDs. The time correction circuit includes two CCDs 2 and 3, a voltage-controlled oscillator (VCO) 4 for generating a common clock pulse signal (hereinafter simply called the "clock") for driving the CCDs, and a time base error detector 5 for detecting the time base error present in the video signal and applying the detected output to the VCO 4.
The regenerative RF input signal consists of a regenerative video signal and a regenerative audio FM signal. The regenerative video signal is demodulated by a video detector 6 before being applied to the CCD 2, whereas the regenerative audio FM signal is applied to the CCD 3. When the regenerative RF input signal has a time base error, the demodulated video signal and the regenerative audio FM signal applied to the CCDs have the same time base error.
The time base error detector 5 detects the time base error present in the video output signal and supplies the detected output to the VCO 4. The VCO 4 produces a clock having a frequency determined by the detected output voltage and applies the clock to the CCDs 2 and 3. These CCDs, being driven by the clock, impart the same delay time to the demodulated video signal and regenerative audio FM signal in directions canceling the time base error common to them to effect time base correction. The output signal of the CCD 2 and that of the CCD 3, which is demodulated by an audio detector 7, are outputted as video and audio signals, respectively.
Assuming that the number of CCD stages, i.e., the number of stages in the transfer section of the CCD, is N and the frequency of the driving clock is f.sub.c (MHz), the CCD delay time T.sub.d (microseconds) is represented by the following equation: EQU T.sub.d =N/f.sub.c. (1)
As is obvious from the above equation, the delay time can be changed by changing the clock frequency f.sub.c.
Assuming that the time base error present in the regenerative RF input signal has a maximum deviation of .DELTA.T.sub.max, the possible variation width .DELTA.T.sub.d max of CCDs 2 and 3 delay time must be .DELTA.T.sub.max or more to successfully subject the demodulated video and regenerative audio FM signals to time base correction.
The variation width .DELTA.T.sub.d of the delay time when thee frequency for driving the N stage CCD is changed from f.sub.1 to f.sub.2 is generally given by the following equations (based on the preceding equation (1): EQU T.sub.d1 =N/f.sub.1, and EQU T.sub.d2 =N/f.sub.2,
where T.sub.d1 =delay time of the CCD corresponding to f.sub.1, and f.sub.2 =clock frequency. If f.sub.1 &lt;f.sub.2, .DELTA.T.sub.d can be represented by: EQU .DELTA.T.sub.d =T.sub.d1 -T.sub.d2 =N/f.sub.1 -N/f.sub.2 =N(1/f.sub.1 -1/f.sub.2). (2)
In the time base correction circuit of FIG. 1, the same time error is present in the demodulated video and the regenerative audio FM signals respectively applied to the CCDs 2 and 3 so that time base correction may be effected by providing the same delay time variation width in the CCDs 2 and 3. In the time base correction circuit 1 of FIG. 1, a clock of the same frequency is supplied to the CCDs 2 and 3 as a common clock from the VCO 4 is used for the CCDs 2 and 3. Consequently, as is evident from equation (2), the number stages of the CCD 2 must be the same as that of the CCD 3 to allow the CCDs 2 and 3 to effect the same delay time variation width.
Further analysis will be made taking an optical video disk player using the
system as an example.
The demodulated video signal applied to the CCD 2 has a frequency range of 0 to 5 MHz, whereas the audio FM signal applied to the CCD 3 employs FM carriers with frequencies of approximately 0.7 and 1.1 MHz. As a result, a signal of a frequency band wider than that for the signal applied to the CCD 3 is applied to the CCD 2, and the highest frequency of the signal applied to the CCD 2 is 5 MHz, whereas that applied to the CCD 3 is 1.1 MHz.
Since a CCD is generally a sampling element, a clock frequency f.sub.c twice or more as high as the highest frequency of the input signal is deemed satisfactory based upon well-known sampling theory; however, the former is normally set three times as high or higher in view of the characteristics of the CCD. Accordingly, the clock frequency for the CCD 2 has only to satisfy: EQU f.sub.c .gtoreq.5.times.3, i.e., f.sub.c .gtoreq.15 MHz, (3)
and that for the CCD: EQU f.sub.c .gtoreq.1.1.times.3, i.e., f.sub.c .gtoreq.3.3 MHz. (4)
In other words, when the maximum deviation .DELTA.T.sub.max of the time base error present in the regenerative RF input signal is subjected to time base correction, the lowest frequency f.sub.min of the clock has only to satisfy equations (3) and (4). When a common clock is used for the CCDs 2 and 3, as in the case of the time base correction circuit 1 of FIG. 1, the lowest frequency f.sub.min of the clock generated by the VCO 4 satisfies equation (3).
A minimum possible value N.sub.min in the number of CCD stages necessary for subjecting to time base correction the maximum deviation .DELTA.T.sub.max of the regenerative RF input signal will now be considered. The highest frequency f.sub.max of the clock may not be set higher without limitation but is limited depending on the performance of the element or the CCD. About 20 MHz is generally considered to be an upper limit in view of present technology. On the basis of equation (2), the possible delay time variation width .DELTA.T.sub.d max for the CCD is thus given by: EQU .DELTA.T.sub.d max =N(1/f.sub.min -1/f.sub.max). (5)
In view of the foregoing, the maximum possible delay time variation width .DELTA.T.sub.d max for the CCD must be greater than the maximum deviation .DELTA.T.sub.d max of the time base error present in the regenerative RF input signal. Assuming that the time base correction circuit 1 is designed to satisfy .DELTA.T.sub.d max =.DELTA.T.sub.max, the minimum number N.sub.min or CCD stages on the basis of equation (5) is expressed by: EQU .DELTA.T.sub.max =N.sub.min (1/f.sub.min -1/f.sub.max). (6)
In equation (6), .DELTA.T.sub.max is set to meet design requirements and f.sub.min is determined by equations (3) and (4), whereas f.sub.max is determined by the performance of the CCD element.
Assuming that the maximum deviation .DELTA.T.sub.max of the RF input signal is 10 microseconds and that the highest frequency f.sub.max of the clock is 20 MHz, equation (6) becomes: EQU 10=N.sub.min-1 (1/f.sub.min -1/20).
If a common clock is not supplied to the CCDs 2 and 3 and instead clocks of different frequencies are supplied thereto, and if N.sub.min-1 and N.sub.min-2 represent minimum numbers of stages of the CCDs 2 and 3 respectively, and f.sub.min =15 MHz (from equation (3)): EQU 10=N.sub.min-1 (1/15-1/20). (7)
Thus, N.sub.min-1 =600.
For f.sub.min =3.3 MHz (from equation (4)), for the CCD 3: EQU 10=N.sub.min-2 (1/3.3-1/20). (8)
Thus, N.sub.min-2 =40.
Accordingly, if clocks of different frequencies are supplied to the CCDs 2 and 3 in the time base correction circuit of FIG. 1, more than 600 and 40 stages should be provided for the CCDs 2 and 3, respectively.
In the time base correction circuit of FIG. 1, however, the number of stages of the CCD 2 must, as above described, be the same as that of the CCD 3 since a common clock is used for the CCDs 2 and 3; that is, they must have more than 600 stages. Consequently, a CCD possessing stages lmore than otherwise necessary is employed for the CCD 3.
The greater the number of stages in the CCD, the greater the chip area generally becomes when the CCD is fabricated in IC form. This results in higher costs and an increase in power consumption.